An instruction set of variable-length instruction code format has a basic segment containing a code identifying type of instructions, and an expanded segment based on the identification in the basic segment. One instruction includes one or more basic segments. The expanded segment's attribute's, such as its presence or absence, length and so forth, are defined by the code in the effective address field contained in the basic segment. The effective address field is inserted immediately after the basic segment by which it is identified. In other words, the basic segment is a portion to be decoded by a decoder, such as a PLA, for the discrimination of instructions. The expanded segment is a data portion generating a displacement value or an immediate value.
FIG. 3(a) is an illustration showing one example of a typical instruction format used in the prior art. This instruction format is frequently established for binary operation. Therefore, discussion will give provided for the binary operation. Basic segments 1 300 and basic segment 2 310 form two basic segments respectively having one unit length (e.g. 2 bytes). Respective basic segments 300 and 310 have effective address fields EA1 504 and EA2 514 respectively identifying source operand and destination operand. Types of instructions are identified by other fields OP1 302 and OP2 312.
The effective address fields 304 and 314 contain encoded information indicating if the operand is a registered, immediate value or data in the memory. When the operand is data in the memory, it also identifies the address calculation method therefor. There are several address calculation methods, for example an absolute address mode identifying an address per se in the expanded segment; a register relative address mode or PC relative address mode adding value of a register or a program counter (PC) to the value of the expanded segment; a SP relative increment mode, in which address calculation and updating of the stack pointer; is performed employing a stack pointer and so forth. It should be noted that the basic segment is provided with a predetermined fixed length per instruction code (the length is variable in different instruction codes).
On the other hand, when the expanded segment is the immediate value, the length is determined according to the operand size. The operand size is assigned as 1 byte, two bytes (half word), four bytes (word) or eight bytes (long word) and so forth. In the case of a one byte immediate value, if the unit length of the instruction code is two bytes, the length becomes insufficient for filling the instruction code. In such a case, extra data (such "O") is added to the upper bite for adapting to the unit length. In the case of memory address identification, the expanded segment is regarded as a displacement value and is used for deriving the address by summing with zero, a register or the PC. In this case, the length of the expanded segment is identified by the effective address field to identify a sixteen bit displacement value, a thirty-two bit displacement value or a sixty-four bit displacement value and so forth. In the case of a SP relative address identification or a register indirect address identification, in which the displacement value is not added, the expanded segment will not be provided. The expanded portion is added immediately after the effective address is filed that identifies the same.
In FIGS. 3(B)-1 through 3(B)- 6, there is illustrated an example of the instruction code string formed with the basic segment and the expanded segment.
In the above-mentioned example, the register is basically formed by the basic segment. The length of the expanded segment arranged following a respective basic segment is illustrated to have the variable length of n times of the unit length L.
Next, an example of the conventional method for performing data processing employing such instruction code string is discussed with reference to FIGS. 4 and 5.
Namely, FIG. 5 shows a register containing the instruction format of immediate value (32 bits). The structure 500 contains the basic segment 1 501 and the expanded segment 1 502 and the basic segment 2 510 that does not have the expanded segment.
As shown in FIG. 4, the instruction code string obtained from an external memory or a cache 1 401 in advance of execution of the instructions, is stored in a data storage portion 3 403 of an instruction buffer 2 402. The storage section 3 403 is formed with a register file or so forth. One entry 4 404 has about a sixteen byte in the case of a sixty-four bits processor and about eight bytes in the case of a thirty-two bits processor. The instruction code string is stored in a plurality of entries 404, 404', 404". . . according to the arrangement of sixteen bytes boundary or eight bytes boundary. The example in FIG. 4 shows an example of the thirty-two bits processor, and thus, the expanded segment having a sixth-four bits length will not be assigned.
The instruction buffer 2 402 is provided with a reading out pointer 7 407 indicative of the leading end of the instruction string to be supplied to an instruction decoder. The pointer 7 407 indicates an entry 404 containing the leading position P1 and the position in the entry using, for example, the program counter. Because of variable length instruction, the leading end of the instruction does not always indicate the 8 byte boundary or sixteen byte boundary. When the leading end is placed at the intermediate position P1, reading out is performed over two entries 404 and 404' (515 in FIG. 5). Therefore, the instruction buffer 2 performs a decoding of the entry 404 by reading per instruction code unit length.
FIG. 5 shows the reading out process.
The code read out takes the structure in a format of a reading out report output. If the code is directly output to the instruction code bus, it makes it difficult to identify the position on the bus to be picked up by the PLA for instruction decoding. Therefore, the code is rotated to place the leading end of the instruction code at the most significant position on the bus and then output 520.
In this case, the position of the second basic segment 2 510 is shifted away because of the presence of the expanded segment for the first effective address, when one instruction is formed with a plurality of basic segments 1 501 and 2 510. Accordingly, although it is easy to decode the first and second segments simultaneously when the first effective address has no expanded segment, if the first effective address has the expanded segment 502, the length of the expanded segment 2 (not shown) cannot be determined until decoded. Therefore, the second basic segment 510 cannot be input to the PLA in order to decode during the same cycle. This requires decoding to be performed separately in several cycles. This implies that, when the source operand is register direct and the destination operand is a memory, they can be decoded in one cycle, whereas even when the instruction code string is the same length, if the source operand is memory data or an the immediate value and the destination operand is the register, it requires two cycles for decoding
An operation between the register and the memory can be decoded at one cycle, if the expanded segment identified by the second basic segment and the expanded segment in which the first basic segment identifies the memory differentiate the relative position from the leading end. However, the hardware required in the immediate and displacement generation circuit is increased.
The present invention is designed to improve the foregoing problems and has an object to provide a buffer means that enables simultaneous decoding even when one instruction is identified by a combination of a plurality of basic segments of instruction codes and a random length of the expanded segment is inserted between the basic segments. Another object of the invention is to minimize an increase in hardware in such a case.